1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device having a high resistive element including a high melting point metal.
2. Description of the Related Art
Recently, a high resistive elemtent has been used as a load of a SRAM memory cell. Such as SRAM memory cell is shown in FIG. 4. FIG. 4 illustrates a circuit construction of a SRAM memory cell composed of the foregoing high resistance load type four transistors. A power supply line 11 for Vcc is connected to direct contacts 15 through high resistance loads 12. The distinctive aspect of this construction lies in that the gate of one driver transistor 16 is directly connected to the drain of the other diver transistor 16 at the direct contact 15. The data come in and out through bit lines 14 and word transistors 13.
FIG. 12 is a sectional view illustrating a construction of a cell in a conventional typical SRAM. Each of the cells in the SRAM is constructed on a silicon substrate 101, which comprises a field oxide film 102 for separating devices, a first conductive layer 104 consisting of source region, drain region, and gate region of the transistor and the like, insulating layers of a silicon oxide film 108 and 112 and a phosphorus glass 113 for insulating the conductive layers, a second conductive layer 401 and 402 of a polysilicon (hereafter, mentioned as poly Si) wiring formed on and through the first insulating layer 108, and a contact 114 connected to an aluminum wiring 115 and the like. Generally, the second conductive layers are formed of the poly Si wiring on a second layer (hereafter, abbreviated as 2 poly), and the high resistance region 402 is used for high resistance devices and a part of the low resistance region 401 is used for the power supply line.
A most widely used method to form the second conductive layers is the division fitting exposure technique whereby the low resistance region and the high resistance region are separately made in non-self matching. Application of this method has required the exposure technique to fit four scale divisions among the direct contact process for directly bringing the gate electrode and diffusion layer into contact, the poly poly contact process for connecting a 2 poly to a poly Si of the gate electrode, the 2 poly forming process, and the 2 poly resistance control process. However, this method takes many processes and the 2 poly formation requires an advanced micro wiring forming technique, and it is difficult to reduce the resistance in the low resistance region of the 2 poly and the 2 poly resistance varies in the subsequent process using the chemical vapor deposition (CVD) method and the like.
In order to decrease the production processes, there have been proposals that reduce the direct contact process or the poly poly contact process by making up the cell construction as shown in FIG. 15(a) or FIG. 15(b). And, in order to improve working accuracy of the 2 poly, increasing the poly Si wiring layer and making a three-dimensional construction can be considered; however, it increases processes to a large extent as well as increases uneven surfaces only to make the subsequent aluminum wiring difficult. In order to overcome these imperfections, there have been disclosed a method whereby a bedding gate unevenness is flattened by means of the chemical mechanical polishing (CMP) before forming the 2 poly wiring so as to improve the working accuracy, a method whereby a high resistance poly Si is formed on the inner wall of a through-hole and the aluminum wiring is electrically connected to the high resistance poly Si in forming the metal contact and load resistors are formed in the contact area, and a method whereby a Si oxide film and Si nitride film are laminated on the bottom of a contact through-hole to use for the high resistance load.
As a measure to prevent the resistance variation of the high resistance loads, a method to form a thermal oxidation film of about 50 Angstrom has been used in practice. This method is used for reducing the charge trapping in the 2 poly CVD oxide film interface and for the barrier against the phosphorous diffusion from the phosphorous glass layer and the like.
Although each of the foregoing methods is effective as a measure to individual problems, it is not effective as a measure to the other problems; or still more advanced technique is required to solve the problem, leaving problems for practical use.
The Japanese Patent Laid-open No. Hei 1-124250 discloses, to solve these problems, a construction in which the inside of the through-hole is filled up with the high resistance poly Si. FIG. 13(a) through FIG. 13(g) and FIG. 14 show the outline of the production method of the construction.
(a) first, a field oxide film 102 of about 7000 angstrom is formed as an element separating film on an N-type Si substrate 101 by means of a well-known method.
(b) next, a gate oxide film 103 of about 300 angstrom is formed, and then a gate poly Si film 104 of about 4000 angstrom is formed into optional wirings.
(c) next, a source and drain layer of the N channel only are formed as a transistor by the well-known method. The SD annealing temperature is 950.degree. C. And afterward, an oxide film of about 4000 angstrom is formed under atmospheric pressure, on which SOG is applied to make the surface flat, and then a through-hole 109 for connecting the second layer wiring to the gate electrode is formed with an opening diameter of about 1.2 .mu.m.
(d) next, a poly Si film 110 of about 1.2 .mu.m is formed as a 2 poly by the reduced pressure CVD method.
(e) next, the poly Si film 110 is removed entirely from the flat layer by means of the etch back. Here, a high resistance poly Si 601 remains inside the through-hole 109 to fill up to the upper side.
(f) next, a poly Si film 602 of about 2500 angstrom is formed, on the whole surface of which arsenic (As) is implanted under 80 keV, 1 exp 16 atoms/cm.sup.2 to lower the resistance of the film.
(g) afterward, the low resistance wiring 602 is patterned, and a phosphorous glass 113, contact 114, and aluminum wiring 115 are formed.
This proposal can solve all the foregoing problems, the construction is simple, and current facilities can be used for the production, which are advantageous in this method. However, there are still problems as follows, concerning the construction in which the inside of the through-hole is filled up with a high resistance poly Si to form a high resistance load.
Since the whole inside of the poly poly contact is made high resistive, the direct contact process cannot be eliminated by a constriction shown in FIG. 15(c). Only the division fitting exposure process for controlling the 2 poly resistance can be removed in the conventional method.
The resistance of the high resistance poly Si formed inside of the through-hole greatly depends on an intrinsic resistance of the poly Si, which makes the resistance control difficult and the matching among production lines difficult.
In case the through-hole diameter is large, it is necessary to deposit the 2 poly so thick as to fill up the hole. Therefore, the etch back process after the 2 poly film formation becomes essential, which invites increase of the process as well as problem of the dependency in the wafer of the 2 poly etching rate.